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In microprocessor design, the main idea behind an architecture with non-sequential dynamic execution scheduling (ANDES) is to preorder processor instructions by their readiness (not necessarily identic to the program order). It means that the instructions are topologically sorted.
Another features include speculative conditional branches and non-blocking Load/Store.
Originally, ANDES was developed for the supercomputers (HP-PA 8000, MIPS R10000, IBM Power 4).
See also: scheduling
